Logic Design Engineer招聘 - 威盛电子（中国）有限公司

【Responsibilities】

1.Logic Design, verification for SOC;

2.Asic flow timing analysis, logical synthesis , system debug.

【Requirements】

1.Bachelor degree or above，Microelectronic or related，0-3 years’experience;

2.Knowledge ASIC design flow,

3.Familiar with Verilog or VHDL;

4.Familiar with chip verification environment and flow, such as CPF/UPF/System verilog;

5.Knowledge one of the following technology: PCIE,SATA, NAND flash controller, DDR2/3 controller;

6.Good team work capability with others.