Logic Design Engineer -北京招聘 - 威盛电子（中国）有限公司

【Responsibilities】

1. Logic design and verification for SOC;

2. Simulation and System debugging; 

3. FPGA/ASIC flow for synthesis, timing analysis and related debugging.

【Requirements】

1. MS in Microelectronic, Electronic Engineering, Computer Science or related;

2. Knowledge of digital circuit design, computer system architecture;

3. Familiar with Verilog or VHDL, and behavior modeling;

4. Experience with FPGA or ASIC design tools, such as Simulator, Synthesis and STA;

5. Knowledge of the following is a plus: DDR, SATA, PCIe, NVMe, Ethernet, Storage System;

6. Good team work capability with others.